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| Order this document by UC3842A/D UC3842A, 43A UC2842A, 43A High Performance Current Mode Controllers The UC3842A, UC3843A series of high performance fixed frequency current mode controllers are specifically designed for off-line and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8-pin dual-in-line plastic package as well as the 14-pin plastic surface mount (SO-14). The SO-14 package has separate power and ground pins for the totem pole output stage. The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally suited for off-line converters. The UCX843A is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). * Trimmed Oscillator Discharge Current for Precise Duty Cycle Control HIGH PERFORMANCE CURRENT MODE CONTROLLERS N SUFFIX PLASTIC PACKAGE CASE 626 8 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) 14 1 * * * * * * * * Current Mode Operation to 500 kHz Automatic Feed Forward Compensation Latching PWM for Cycle-By-Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis Low Startup and Operating Current Direct Interface with Motorola SENSEFET Products PIN CONNECTIONS Compensation 1 Voltage Feedback 2 Current Sense 3 RT/CT 4 (Top View) 8 7 6 5 Vref VCC Output Gnd Compensation NC Voltage Feedback NC Current Sense 1 2 3 4 5 6 7 (Top View) 14 Vref 13 NC 12 VCC 11 VC 10 Output 9 8 Gnd Power Ground Simplified Block Diagram VCC Vref 8(14) R R RTCT 4(7) Voltage Feedback Input 2(3) Output Compensation 1(1) + - NC RT/CT 7(12) 5.0V Reference Vref Undervoltage Lockout Oscillator Latching PWM Error Amplifier VCC Undervoltage Lockout VC 7(11) Output 6(10) Power Ground 5(8) Current Sense 3(5) Input ORDERING INFORMATION Device UC3842AD UC3843AD UC3842AN UC3843AN UC2842AD UC2843AD UC2842AN UC2843AN (c) Motorola, Inc. 1996 Operating Temperature Range Package SO-14 TA = 0 to +70C SO-14 Plastic Plastic SO-14 Gnd 5(9) TA = - 25 to +85C SO-14 Plastic Plastic Rev 1 Pin numbers in parenthesis are for the D suffix SO-14 package. MOTOROLA ANALOG IC DEVICE DATA 1 UC3842A, 43A UC2842A, 43A MAXIMUM RATINGS Rating Total Power Supply and Zener Current Output Current, Source or Sink (Note 1) Output Energy (Capacitive Load per Cycle) Current Sense and Voltage Feedback Inputs Error Amp Output Sink Current Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air N Suffix, Plastic Package Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature UC3842A, UC3843A UC2842A, UC2843A Storage Temperature Range Symbol (ICC + IZ) IO W Vin IO Value 30 1.0 5.0 - 0.3 to + 5.5 10 Unit mA A J V mA PD RJA PD RJA TJ TA 862 145 1.25 100 + 150 0 to + 70 - 25 to + 85 mW C/W W C/W C C Tstg - 65 to + 150 C ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3], unless otherwise noted.) UC284XA Characteristics REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25C) Line Regulation (VCC = 12 V to 25 V) Load Regulation (IO = 1.0 mA to 20 mA) Temperature Stability Total Output Variation over Line, Load, Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25C) Long Term Stability (TA = 125C for 1000 Hours) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = 25C TA = Tlow to Thigh Frequency Change with Voltage (VCC = 12 V to 25 V) Frequency Change with Temperature TA = Tlow to Thigh Oscillator Voltage Swing (Peak-to-Peak) Discharge Current (Vosc = 2.0 V) TJ = 25C TA = Tlow to Thigh fosc 47 46 fosc/V fosc/T Vosc Idischg 7.5 7.2 8.4 - 9.3 9.5 7.5 7.2 8.4 - 9.3 9.5 - - - 52 - 0.2 5.0 1.6 57 60 1.0 - - 47 46 - - - 52 - 0.2 5.0 1.6 57 60 1.0 - - % % V mA kHz Vref Regline Regload TS Vref Vn S ISC 4.95 - - - 4.9 - - - 30 5.0 2.0 3.0 0.2 - 50 5.0 - 85 5.05 20 25 - 5.1 - - - 180 4.9 - - - 4.82 - - - 30 5.0 2.0 3.0 0.2 - 50 5.0 - 85 5.1 20 25 - 5.18 - - - 180 V mV mV mV/C V V mV mA Symbol Min Typ Max Min UC384XA Typ Max Unit NOTES: 1. Maximum Package power dissipation limits must be observed. 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible Tlow = -20C for UC3842A, UC3843A Thigh = +70C for UC3842A, UC3843A Tlow = -25C for UC2842A, UC2843A Thigh = +85C for UC2842A, UC2843A 2 MOTOROLA ANALOG IC DEVICE DATA UC3842A, 43A UC2842A, 43A ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3], unless otherwise noted.) UC284XA Characteristics ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 2.7 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25C) Power Supply Rejection Ratio (VCC = 12 V to 25 V) Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 4 & 5) Maximum Current Sense Input Threshold (Note 4) Power Supply Rejection Ratio VCC = 12 to 25 V (Note 4) Input Bias Current Propagation Delay (Current Sense Input to Output) OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) Low State (ISink = 200 mA) High State (ISink = 20 mA) High State (ISink = 200 mA) Output Voltage with UVLO Activated VCC = 6.0 V, ISink = 1.0 mA Output Voltage Rise Time (CL = 1.0 nF, TJ = 25C) Output Voltage Fall Time (CL = 1.0 nF, TJ = 25C) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX842A UCX843A Minimum Operating Voltage After Turn-On UCX842A UCX843A PWM SECTION Duty Cycle Maximum Minimum TOTAL DEVICE Power Supply Current (Note 2) Startup: (VCC = 6.5 V for UCX843A, (VCC = 14 V for UCX842A) Operating Power Supply Zener Voltage (ICC = 25 mA) ICC - - VZ 30 0.5 12 36 1.0 17 - - - 30 0.5 12 36 1.0 17 - V mA % DCmax DCmin 94 - 96 - - 0 94 - 96 - - 0 Vth 15 7.8 VCC(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 V V V VOL VOH VOL(UVLO) - tr tf - - 0.1 50 50 1.1 150 150 - - - 0.1 50 50 1.1 150 150 ns ns - - 13 12 0.1 1.6 13.5 13.4 0.4 2.2 - - - - 13 12 0.1 1.6 13.5 13.4 0.4 2.2 - - V AV Vth PSRR IIB tPLH(in/out) 2.85 0.9 - - - 3.0 1.0 70 -2.0 150 3.15 1.1 - -10 300 2.85 0.9 - - - 3.0 1.0 70 -2.0 150 3.15 1.1 - -10 300 A ns V/V V dB VFB IIB AVOL BW PSRR ISink ISource VOH VOL 2.45 - 65 0.7 60 2.0 -0.5 5.0 - 2.5 -0.1 90 1.0 70 12 -1.0 6.2 0.8 2.55 -1.0 - - - - - - 1.1 2.42 - 65 0.7 60 2.0 -0.5 5.0 - 2.5 -0.1 90 1.0 70 12 -1.0 6.2 0.8 2.58 -2.0 - - - - - V - 1.1 V A dB MHz dB mA Symbol Min Typ Max Min UC384XA Typ Max Unit NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible Tlow = -20C for UC3842A, UC3843A Thigh = +70C for UC3842A, UC3843A Tlow = -25C for UC2842A, UC2843A Thigh = +85C for UC2842A, UC2843A 4. This parameter is measured at the latch trip point with VFB = 0 V. V Output Compensation 5. Comparator gain is defined as: AV V Current Sense Input MOTOROLA ANALOG IC DEVICE DATA 3 UC3842A, 43A UC2842A, 43A Figure 1. Timing Resistor versus Oscillator Frequency 80 50 RT, TIMING RESISTOR (k ) 20 8.0 5.0 2.0 VCC = 15 V TA = 25C 0.8 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M % DT, PERCENT OUTPUT DEADTIME 100 50 20 10 5.0 2.0 1.0 VCC = 15 V TA = 25C Figure 2. Output Deadtime versus Oscillator Frequency 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (Hz) fOSC, OSCILLATOR FREQUENCY (Hz) Figure 3. Oscillator Discharge Current versus Temperature 9.0 I dischg , DISCHARGE CURRENT (mA) VCC = 15 V VOSC = 2.0 V 8.5 Dmax , MAXIMUM OUTPUT DUTY CYCLE (%) 100 90 80 70 60 50 40 800 Figure 4. Maximum Output Duty Cycle versus Timing Resistor VCC = 15 V CT = 3.3 nF TA = 25C Idischg = 7.2 mA 8.0 7.5 Idischg = 9.5 mA 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k 7.0 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 RT, TIMING RESISTOR () Figure 5. Error Amp Small Signal Transient Response VCC = 15 V AV = -1.0 TA = 25C Figure 6. Error Amp Large Signal Transient Response VCC = 15 V AV = -1.0 TA = 25C 2.55 V 3.0 V 20 mV/DIV 2.5 V 2.5 V 2.45 V 0.5 s/DIV 2.0 V 0.1 s/DIV 4 MOTOROLA ANALOG IC DEVICE DATA 200 mV/DIV UC3842A, 43A UC2842A, 43A Figure 7. Error Amp Open Loop Gain and Phase versus Frequency A VOL , OPEN LOOP VOLTAGE GAIN (dB) 100 80 Gain 60 40 Phase 20 0 120 150 100 1.0 k 10 k 100 k 1.0 M 180 10 M VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K TA = 25C Vth, CURRENT SENSE INPUT THRESHOLD (V) 0 30 60 90 EXCESS PHASE (DEGREES) , 1.2 VCC = 15 V 1.0 0.8 0.6 TA = 125C 0.4 0.2 0 TA = -55C TA = 25C Figure 8. Current Sense Input Threshold versus Error Amp Output Voltage - 20 10 0 f, FREQUENCY (Hz) 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (V) 8.0 ISC, REFERENCE SHORT CIRCUIT CURRENT (mA) V ref , REFERENCE VOLTAGE CHANGE (mV) Figure 9. Reference Voltage Change versus Source Current 0 VCC = 15 V Figure 10. Reference Short Circuit Current versus Temperature 110 VCC = 15 V RL 0.1 90 -4.0 -8.0 -12 -16 -20 -24 0 20 40 60 80 100 120 Iref, REFERENCE SOURCE CURRENT (mA) TA = 125C TA = 25C 70 TA = 55C 50 -55 -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) VCC = 15 V IO = 1.0 mA to 20 mA TA = 25C , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 11. Reference Load Regulation Figure 12. Reference Line Regulation VCC = 12 V to 25 V TA = 25C O V 2.0 ms/DIV V MOTOROLA ANALOG IC DEVICE DATA O 2.0 ms/DIV 5 UC3842A, 43A UC2842A, 43A Figure 13. Output Saturation Voltage versus Load Current V sat , OUTPUT SATURATION VOLTAGE (V) 0 VCC Figure 14. Output Waveform VCC = 15 V CL = 1.0 nF TA = 25C -1.0 -2.0 Source Saturation (Load to Ground) TA = 25C TA = -55C VCC = 15 V 80 s Pulsed Load 120 Hz Rate 90% 3.0 TA = -55C 2.0 1.0 0 0 Sink Saturation (Load to VCC) TA = 25C Gnd 10% 200 400 600 IO, OUTPUT LOAD CURRENT (mA) 800 50 ns/DIV V O , OUTPUT VOLTAGE Figure 15. Output Cross Conduction VCC = 30 V CL = 15 pF TA = 25C 25 20 V/DIV I CC , SUPPLY CURRENT (mA) 20 15 10 UCX843A 5 0 100 ns/DIV 0 Figure 16. Supply Current versus Supply Voltatage I CC , SUPPLY CURRENT 100 mA/DIV RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25C 20 30 40 10 6 MOTOROLA ANALOG IC DEVICE DATA UCX842A VCC , SUPPLY VOLTAGE UC3842A, 43A UC2842A, 43A Figure 17. Representative Block Diagram VCC VCC 7(12) 36V + - VC Vref UVLO TQ 1.0mA S 2R R 1.0V Current Sense Comparator Gnd 5(9) + - = - + Q R PWM Latch 7(11) Output 6(10) Power Ground 5(8) Current Sense Input 3(5) RS Q1 Vin Vref 8(14) R 2.5V RT R 3.6V Oscillator 4(7) CT Voltage Feedback Input 2(3) Output Compensation 1(1) + - Error Amplifier + Internal Bias Reference Regulator + +- - + VCC UVLO - Sink Only Positive True Logic Pin numbers in parenthesis are for the D suffix SO-14 package. Figure 18. Timing Diagram Capacitor CT Latch ``Set'' Input Output/ Compensation Current Sense Input Latch ``Reset'' Input Output Large RT/Small CT Small RT/Large CT MOTOROLA ANALOG IC DEVICE DATA 7 UC3842A, 43A UC2842A, 43A OPERATING DESCRIPTION The UC3842A, UC3843A series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off-Line and dc-to-dc converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 17. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates and internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within 10% at TJ = 25C. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 3 and 4. In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking, the free-running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 21. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 7). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0 A which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 30). The output voltage is offset by two diode drops ( 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figures 23, 24). The Error Amp minimum feedback resistance is limited by the amplifier's source current (0.5 mA) and the required output voltage (VOH) to reach the comparator's 1.0 V clamp level: Rf(min) 3.0 (1.0 V) + 1.4 V = 8800 0.5 mA Current Sense Comparator and PWM Latch The UC3842A, UC3843A operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin1). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: V - 1.4 V Ipk = (Pin 1) 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: 1.0 V RS Ipk(max) = When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 26. 8 MOTOROLA ANALOG IC DEVICE DATA UC3842A, 43A UC2842A, 43A PIN FUNCTION DESCRIPTION Pin 8-Pin 1 2 3 4 5 6 7 8 - - 14-Pin 1 3 5 7 - 10 12 14 8 11 Function F i Compensation Voltage Feedback Current Sense RT/CT Gnd Output VCC Vref Power Ground VC Description D ii This pin is Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. This pin is the combined control circuitry and power ground (8-pin package only). This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through resistor RT. This pin is a separate power ground return (14-pin package only) that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin (14-pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This pin is the control circuitry ground return (14-pin package only) and is connected back to the power source ground. No connection (14-pin package only). These pins are not internally connected. - - 9 2,4,6,13 Gnd NC Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842A, and 8.4 V/7.6 V for the UCX843A. The Vref comparator upper and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of the UCX842A makes it ideally suited in off-line converter applications where efficient bootstrap startup techniques are required (Figure 33). The UCX843A is intended for lower voltage dc to dc converter applications. A 36 V zener is connected as a shunt regulator form VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX842A is 11 V and 8.2 V for the UCX843A. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to 1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull-down resistor. The SO-14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater that 20 V. Figure 25 shows proper power and control ground connections in a current sensing power MOSFET application. Reference The 5.0 V bandgap reference is trimmed to 1.0% tolerance at TJ = 25C on the UC284XA, and 2.0% on the UC384XA. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. MOTOROLA ANALOG IC DEVICE DATA 9 UC3842A, 43A UC2842A, 43A DESIGN CONSIDERATIONS Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. High Frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 F) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed-loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2 until the next oscillator cycle. The unstable condition can be shown if a pertubation is added to the control voltage, resulting in a small I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn-on (t2) is increased by I + I m2/m1. The minimum current at the next cycle (t3) decreases to (I + I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn-on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 19B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the I pertubation will decrease to zero on succeeding cycles. This compensation ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32). Figure 19. Continuous Current Waveforms I Control Voltage m2 m1 Inductor Current t0 I + I m2 m1 t1 t2 m2 I + I m 1 m2 m1 t3 (A) Oscillator Period (B) Control Voltage I m3 m1 m2 Oscillator Period t4 t5 Inductor Current t6 10 MOTOROLA ANALOG IC DEVICE DATA UC3842A, 43A UC2842A, 43A Figure 20. External Clock Synchronization Vref 8(14) RT R Bias R Osc 0.01 CT 47 4(7) + - 2(3) 1(1) 5(9) The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. 1.44 f= (RA + 2RB)C RB Dmax = RA + 2RB EA + 5.0k 5 2 2R R C RA 8 RB 6 5.0k + - + - 4 8(14) R Bias R Osc Q S 3 7 2(3) 1(1) To Additional UCX84XA's 5(9) 4(7) + - EA + Figure 21. External Duty Cycle Clamp and Multi Unit Synchronization External Sync Input R 5.0k MC1455 1 2R R Figure 22. Adjustable Reduction of Clamp Level VCC 7(12) + - Vin Figure 23. Soft-Start Circuit 5.0Vref 8(14) R Bias R Osc 4(7) R2 2(3) 1(1) 5(9) 1.67 R2 +1 R1 R1 R2 R1 + R2 + - EA + 1.0mA 2R R - + 1.0V R1 + - VClamp S + - 5.0Vref + - 7(11) Q1 6(10) 4(7) + - 2(3) 1.0M RS C 1(1) tSoft-Start EA + 1.0mA 2R R S - + 1.0V R Q Osc 8(14) R Bias R + - + - R Comp/Latch Q 5(8) 3(5) 3600C in F 5(9) VClamp = + 0.33 x 10 - 3 Ipk(max) = VClamp RS Where: 0 VClamp 1.0 V Figure 24. Adjustable Buffered Reduction of Clamp Level with Soft-Start VCC 7(12) + - Vin Figure 25. Current Sensing Power MOSFET VCC (12) + - RS Ipk rDS(on) VPin 5 = rDM(on) + RS If: SENSEFET = MTP10N10M RS = 200 Then: Vpin 5 = 0.075 Ipk D SENSEFET Vin S M K 5.0Vref 8(14) R Bias R Osc 4(7) + - 2(3) R2 1(1) C MPSA63 R1 VClamp = 1.67 R2 +1 R1 5(9) Ipk(max) = VClamp RS tSoftstart = - In + 1.0mA EA 2R R + - VClamp - + 1.0V + - 5.0Vref + - 7(11) Q1 6(10) + - + - + - (11) (10) G S Q R Comp/Latch 5(8) 3(5) RS S Q - R + Comp/Latch (8) (5) Power Ground To Input Source Return Control CIrcuitry Ground: To Pin (9) RS 1/4 W Where: 0 VClamp 1.0 V 1- VC 3VClamp C R1 R2 R1 + R2 Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24. MOTOROLA ANALOG IC DEVICE DATA 11 UC3842A, 43A UC2842A, 43A Figure 26. Current Waveform Spike Suppression VCC 7(12) + - Vin Figure 27. MOSFET Parasitic Oscillations VCC 7(12) + - Vin 5.0Vref + - + - 5.0Vref + - + - 7(11) Rg 6(10) Q1 + - + 7(11) Q1 6(10) - - + Q R Comp/Latch S 5(8) R 3(5) C RS - + Q R Comp/Latch S 5(8) 3(5) RS The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Figure 28. Bipolar Transistor Drive IB + 0 - Base Charge Removal C1 Q1 6(1) 5(8) 3(5) RS The totem-pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. Vin Figure 29. Isolated MOSFET Drive VCC 7(12) + - Isolation Boundary Q1 + 0 - VGS Waveforms Vin 5.0Vref + - + - + - 7(11) 6(1) 50% DC S Q - R + Comp/Latch 5(8) R 3(5) C RS NS V(pin 1) - 1.4 Ipk = 3 RS Np Figure 30. Latched Shutdown Figure 31. Error Amplifier Compensation From VO Ri 2(3) CI Rf 1(1) 5(9) 2.5V + - EA + 1.0mA 2R R 8(14) R Bias R Osc Rd 4(7) + - 2(3) 1(1) MCR 101 2N 3905 2N 3903 + 1.0mA EA 2R R Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. From VO 5(9) Rp Cp Ri Rd CI 2(3) Rf 1(1) 5(9) 2.5V + - EA + 1.0mA 2R R The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 12 MOTOROLA ANALOG IC DEVICE DATA EEEE EEEEE EE + 0 - 25% DC NP NS UC3842A, 43A UC2842A, 43A Figure 32. Slope Compensation VCC 7(12) 8(14) 5.0Vref RT MPS3904 R RSlope From VO Ri Cf 4(7) Osc CT 2(3) Rf 1(1) -3.0 m 5(9) + - Vin + - R + - 7(11) Bias + - + 1.0mA -m S 2R R - + + - 6(10) Q EA R 5(8) Rd 1.0V m Comp/Latch 3(5) RS The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Figure 33. 27 Watt Off-Line Flyback Regulator 4.7 115Vac MDA 202 + 4.7k 56k 3300pF MBR1635 T1 2200 MUR110 1N4935 7(12) 8(14) 5.0Vref 0.01 Bias 10k 4(7) Osc 4700pF 18k 2(3) 100pF 150k 4.7k + - + - L1 + 1000 + 5.0V/4.0A 5.0V RTN + L2 10 + 12V/0.3A 12V RTN 250 1N4935 1000 + 47 1000 + 100 68 + - + 10 + + 1N4937 MUR110 680pF 2.7k 22 6(10) MTP 4N50 L3 -12V/0.3A + 7(11) 1N4937 + S EA - + Q R Comp/Latch 5(8) 3(5) 1.0k 470pF 0.5 L1 - 15 H at 5.0 A, Coilcraft Z7156. L2, L3 - 25 H at 1.0 A, Coilcraft Z7157. T1 - Primary: 45 Turns # 26 AWG T1 - Secondary 12 V: 9 Turns # 30 AWG T1 - (2 strands) Bifiliar Wound T1 - Secondary 5.0 V: 4 Turns (six strands) T1 - #26 Hexfiliar Wound T1 - Secondary Feedback: 10 Turns #30 AWG T1 - (2 strands) Bifiliar Wound T1 - Core: Ferroxcube EC35-3C8 T1 - Bobbin: Ferroxcube EC35PCB1 T1 - Gap 0.01" for a primary inductance of 1.0 mH 1(1) 5(9) Test Line Regulation: 5.0 V 12 V Conditions Vin = 95 Vac to 130 Vac Vin = 115 Vac, Iout = 1.0 A to 4.0 A Vin = 115 Vac, Iout = 100 mA to 300 mA Vin = 115 Vac Vin = 115 Vac Results = 50 mV or 0.5% = 24 mV or 0.1% = 300 mV or 3.0% = 60 mV or 0.25% 40 mVpp 80 mVpp 70% Load Regulation: 5.0 V 12 V Output Ripple: Efficiency 5.0 V 12 V All outputs are at nominal load currents, unless otherwise noted. MOTOROLA ANALOG IC DEVICE DATA 13 UC3842A, 43A UC2842A, 43A OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K -B- 1 4 8 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M -A- 14 8 D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F -B- 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 14 *UC3842A/D* MOTOROLA ANALOG IC DEVICE DATA UC3842A/D |
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